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RD_BUSY_MASTER and WR_BUSY_MASTER Operation
The RD_BUSY_MASTER and WR_BUSY_MASTER inputs can be used to prevent a DMA operation from starting
until the backend is able to accept or provide data. For instance, these inputs could be tied to FIFO empty and almost
full flags, respectively. In this case, DMA read transfers would not be started if an external FIFO were empty, and DMA
write transfers would not be started if an external FIFO were almost full.
If multiple memory interfaces are implemented, each with a FIFO, the DMA_BAR output indicates which BAR
memory space the DMA controller is accessing. The appropriate FIFO empty signal should be multiplexed onto the
RD_BUSY_MASTER input; likewise for WR_BUSY_MASTER.
Figure 6-43 shows a DMA read cycle in which RD_BUSY_MASTER is initially active. When it goes inactive (cycle
R0) the core starts the DMA cycle by asserting the PCI bus request in cycle R1. The DMA transfer then progresses
normally.
cycle
R0
R1
A0
A1
A2
A3
0
1
2
3
4
5
6
7
8
9
clk
framen
cben[3:0]
7
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
stopn
reqn
gntn
mast_active
dp_start
dp_done
rd_cyc
bar_select[2:0]
rd_stb_in
rd_stb_out
rd_busy_master
0
mem_add[11:0]
000
004 008
00C 010
014
mem_data_in[31:0]
0
1
2
3
4
5
rd_sync
Figure 6-43 · RD_BUSY_MASTER Operation
92
v4.0
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